A Complete Design Flow for Synthesis and Optimization of Asynchronous Digital Systems

Synchronous hardware design is facing significant challenges as we push for higher clock speeds and more complex chips. Aside from the incredible task of optimizing designs year after year, physical properties of circuits at the current scale and speed are becoming major roadblocks. For example, skew associated with high-fanout clock signals put a great burden the designer by increasing design time, transistor variability reduces the yield of chips at fabrication, and energy consumption at low process sizes and billions of transistors burdens the consumer (as well as the environment). Because of variability, designers must either slow chips by introducing large safety margins or contend with lower yields.